The present invention relates generally to integrated circuit devices and, more particularly, to a corrosion-resistant electrode structure for integrated circuit decoupling capacitors used in non-hermetic environments.
As ultra large-scale integrated (ULSI) circuits have continued to evolve, they have become more complex with respect to switching more and more output driver circuits at higher and higher speeds. In addition, an increase in the use of parallel processing has resulted in the design of integrated circuits with a high number of driver circuits to switch simultaneously at fast transition speeds and high currents. Since the effective inductance of semiconductor chips for these active switching circuits is directly related to the amount of power distribution noise, the driver circuit power connections are particularly sensitive to the noise created by the effective inductance inherent in simultaneous switching activity.
This effective inductance can be lowered by connecting decoupling capacitors in proximity to an integrated circuit (IC). Since inductance is a function of current path length, the shorter the current path, the lower the inductance. High inductance, which yields higher supply noise in semiconductor packages, reduces the performance of ICs. Decoupling capacitors placed close to power consuming circuits are able to smooth out voltage variation with a stored charge thereon. The stored charge may be dissipated, or may also be used as a local power supply to device inputs during signal switching stages, thereby allowing the decoupling capacitor to negate the effects of voltage noise induced into the system by parasitic inductance.
Decoupling capacitors have been provided as discrete components on integrated circuit chip carriers (i.e., modules which carry either single or multiple IC chips). Such decoupling capacitors provided xe2x80x9coff chipxe2x80x9d arc typically mounted upon a packaging substrate by means of solder ball pads (also known in the art as C4 technology) formed upon the electrode interconnect metallurgy of the capacitor body. Typically, this interconnect metallurgy includes a copper layer to provide sufficient electrical conductivity between the capacitor and the substrate. Although copper is a suitable conductive metal for a decoupling capacitor electrode structure in a hermetic environment, there are also applications in which IC modules are operated in non-hermetic environments. In this case, the metallurgy (i.e., copper) of a conventional electrode structure is subject to corrosive effects and, accordingly, structural weakening of the interconnection between the capacitor and the substrate.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by an electrode structure for interconnecting a decoupling capacitor to a substrate. In an exemplary embodiment of the invention, the electrode structure includes a first chromium layer formed upon the capacitor and a first nickel layer formed upon the first chromium layer. A noble metal conductive layer is then formed upon the first nickel layer and a second nickel layer is formed upon said noble metal conductive layer. The second nickel layer has a thickness which is greater than a thickness of the first nickel layer. A second chromium layer is then formed upon the nickel layer.
In a preferred embodiment, the noble metal conductive layer is a gold layer which is about 2,500 xc3x85 in thickness. The first and second chromium layers are each about 1,500 xc3x85 in thickness. The first nickel layer is about 1,000 xc3x85 in thickness, and the second nickel layer is at least 5,000 xc3x85 in thickness, and preferably is about 6,000 xc3x85 in thickness.